We focus on optimizing integrated circuits and systems for high-performance computing.
2T eDRAM PIM
Nov. (65-nm T)'24
3T eDRAM PIM
Nov. (65-nm T)'24
PI ADPLL
Oct. (65-nm T)'24
ILO-based PUF
Oct. (65-nm T)'24
ADC DSP RX
Oct. (40-nm T)'24
Oversampling PLL
Oct. (40-nm T)'24
3T eDRAM PIM
Jul (28-nm S)'24
2T eDRAM PIM
May (65-nm T)'24
ILO-based PUF
May (65-nm T)'24
PI-based CDR
June (28-nm T)'24
TI SAR ADC
June (28-nm T)'24
Supply Noise Insensitive ADPLL
Dec (65-nm T)'23
ADPLL ILO Calibration
Dec (65-nm T)'23
SRAM PIM Accelerator
Dec (65-nm T)'23
Adaptive Gain Controlled DPLL
Dec (65-nm T)'23
TX-PAM4-DRV
July (28-nm S)'23
High-Speed Equalizer
July (28-nm S)'23
ADPLL
Jan (28-nm S)'23
Injection Lock Oscillator (ILO)
Jan (28-nm S)'23
Flash ADC
Jan (28-nm S)'23
Clock Generator
ISSCC'17, JSSC'21
Clock and Data Recovery (CDR)
VLSI'19, JSSC'21
Clock Generator
TCAS-II'19
Power Regulator
ISSCC'19, SSC-L'19
CDR
ASSCC'18, JSSC'19
Clock Generator
TCAS-II'18
Video Interface Receiver
TCAS-II'17
Clock Generator
JSTS'16
Clock Generator
ESSCIRC'15, TCAS-I'18
Clock Gen. & CDR
Failed'17
CDR
Failed'16
CDR
Failed'15
In-Woo Jang (M.S. @ KAIST)
Geun-Young Yoo (M.S.-Ph.D. @ Hanyang University)
Tae-Hyun Kim (M.S.-Ph.D. @ POSTECH)
Seung-Wan Han (ASML)
Woo-Suk Jung (M.S. @ Yonsei University)
Dong-Eun Lee (SK Hynix)
Yu-Jin Byeon (M.S. @ KAIST)
Min-Gwon Song (M.S. @ Hanyang University)
Shin-Uk Kang (Ph.D. @ KAIST)
Ji-Ho Kim (4Lynx)
Kyu-Ran Park (LX semicon)