High-Performance Integrated Circuits

HPIC Design Lab @ Yonsei

The HPIC Lab at Yonsei University designs integrated circuits and systems that push the limits of bandwidth and energy efficiency for AI and high-performance computing. Our core expertise lies in 100–200 Gb/s electrical/optical SerDes and DSP-based transceivers, die-to-die (chiplet) interconnects, and low-jitter clocking circuits (PLL/CDR), complemented by research on AI accelerators and compute-in-memory. By co-optimizing analog, digital, and algorithms, we deliver silicon-proven solutions.

100–200Gb/s SerDes DSP-Based TRX Die-to-Die / Chiplet PLL · CDR AI Accelerator · CIM

Join Us

Last updated · Jul 2026

Please read before joining HPIC Design Lab.

Researchers who collaborate. Our work spans analog, digital, and algorithms, so no one can do it all alone. We prefer students who work naturally with colleagues and, when needed, aren’t afraid to ask for outside help.
A clear growth path. New members progress through basic analog exercises (SPICE) → advanced architecture modeling (SystemVerilog) → real circuit/system design, on a topic you choose or are assigned.
Conferences, encouraged and funded. The lab supports conference activity and covers the costs. For submissions to top-tier circuit venues such as ISSCC and VLSI, an additional stipend is provided.
Hands-on from day one. Funded projects are currently full, so you may take on project-related research and administrative work as soon as you join.
Industry & institute collaboration. Some projects run jointly with industry partners and research institutes, and may require on-site design work at the company or institute (Pangyo / Seoul).

Lab Gallery

High-Performance Integrated Circuits (HPIC)

We focus on optimizing integrated circuits and systems for high-performance computing.

Research Projects

Ongoing and completed research projects.

Chip Gallery

Representative silicon prototypes.

Principal Investigator

M.S.-Ph.D. Candidates

M.S. Candidates

Researchers

Alumni

Teaching

SerDes Lecture Series (A–L) 🔒 Members only

High-speed link lecture series covering the full SerDes stack — slides with fully reproducible simulation code for every figure.

Part I. How the Simulators Work — SPICE, SystemVerilog/Verilog-A, co-simulation (A–C)
Part II. Physics & Measurement — transmission lines, channel ISI & eye, measurement (D–F)
Part III. From the RNM Channel to the DSP Receiver — equalization, PAM, DSP RX, MLSD, ADC (G–L)

Open on GitHub →