Lab Policy

Please read before joining HPIC Design Lab.
  • Recommend working at the office with colleagues (No regulations on working hours).
  • In the first year, don’t worry too much about the chores you may have in the funded project. Rather than being in an active project, make your own chip (any tiny building blocks are fine) work and submit your manuscript to wherever it takes; you must understand the entire process (or goal) in the first year.
  • Bonus credit will be given if your manuscripts are accepted in the following: IEEE ISSCC/VLSI and IEEE JSSC.(another proceedings or journals could be added afterward.)
  • Tutorials on necessary skills in HPIC will be given as lectures or recorded videos. (how to model PLL, CDR, and Transceivers in Verilog language, write script code for efficient simulations, etc.)

HPIC in Media

"학부생 논문이 국제 학술대회에 등재... 전자공학부 학생들의 이례적인 성과"
"대한전자공학회 ICT 백과사전 - 통신용 회로 및 시스템 (한양대학교 추민성 교수)"

Research

High-Performance Integrated Circuits(HPIC)

We focus on optimizing integrated circuits and systems for high-performance computing.

Chip Gallery
Click for more details

2T eDRAM PIM

May (65-nm T)'24

ILO-based PUF

May (65-nm T)'24

PI-based CDR

June (28-nm T)'24

TI SAR ADC

June (28-nm T)'24

Supply Noise Insensitive ADPLL

Dec (65-nm T)'23

ADPLL ILO Calibration

Dec (65-nm T)'23

SRAM PIM Accelerator

Dec (65-nm T)'23

Adaptive Gain Controlled DPLL

Dec (65-nm T)'23

TX-PAM4-DRV

July (28-nm S)'23

High-Speed Equalizer

July (28-nm S)'23

ADPLL

Apr (28-nm S)'23

ADPLL

Jan (28-nm S)'23

Injection Lock Oscillator (ILO)

Jan (28-nm S)'23

Flash ADC

Jan (28-nm S)'23

Clock Generator

ISSCC'17, JSSC'21

Clock and Data Recovery (CDR)

VLSI'19, JSSC'21

Clock Generator

TCAS-II'19

Power Regulator

ISSCC'19, SSC-L'19

CDR

ASSCC'18, JSSC'19

Clock Generator

TCAS-II'18

Video Interface Receiver

TCAS-II'17

Clock Generator

JSTS'16

Clock Generator

ESSCIRC'15, TCAS-I'18

Clock Gen. & CDR

Failed'17

CDR

Failed'16

CDR

Failed'15

Research Projects & Sponsors

  • Apr. 2024 - Mar. 2027

    Development of High-Speed, Low-Power, and Low-Noise Clocking Network Systems for Optical Communication Chiplets

  • Apr. 2022 - Dec. 2024

    Development of low-power/high-performance 2T DRAM PIM cell, integrated circuits, and architecture

  • Sep. 2022 - Sep. 2023

    Design Methodology of High-Performance Integrated Circuits based on Reinforcement Learning

    , completed

  • Sep. 2022 - Sep. 2023

    Development of High PSRR Low Phase Noise Voltage-Controlled Oscillator (VCO)

    , completed

  • Jul. 2022 - Feb. 2025

    반도체전공트랙사업

  • Mar. 2022 - Aug. 2027

    BK21 (고신뢰성 에너지용 지능형 시스템반도체 교육연구단)

  • Mar. 2022 - Dec. 2025

    AI Hardware Center (인공지능 반도체 융합연구센터)

  • Sep. 2022 - Feb. 2024

    강화학습 기반 고성능 아날로그 집적회로 설계 및 측정 플랫폼 개발

    , completed

  • Mar. 2022 - Feb. 2023

    신임교원 정착연구지원사업

    , completed

  • 전력반도체 인력 양성센터

    ...

People

Principal Investigator

minseong-chu-profile-img

Minseong Choo

Assistant Professor

Research Interests

  • High-Speed Interface Design
  • Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) Circuits
  • Injection-Locked Oscillator (ILO)
  • Neuromorphic Computing
  • In-Memory Computing (IMC)
  • Processing-In-Memory (PIM)
  • Optical Transceiver
  • Script-Based Design/Measurement Automation

Details

I serve as a reviewer for various journals, including the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I/II, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and IEEE ACCESS.

Ph.D./M.S. Students

Open Positions

Open PositionsPlease contact to Min-Seong (mschoo@hanyang.ac.kr).
And, think about your future after receiving a degree; Ph.D./Postdoc at HPIC, Ph.D./Postdoc at another institution (domestic/international), and finding a job (domestic/international).

M.S.-Ph.D. Candidates

Shin-Uk Kang

Research Interests AI hardware design and PIM

Tape-out Schedule2023.12 (65-nm T), 2024.05 (28-nm T)

AchievementsICEIC'23, ICEIC'24

DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S -Ph.D. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Email ksu2068@hanyang.ac.kr

Kang-Min Kim

Research Interests Physically Unclonable Function (PUF)

Tape-out Schedule2024.05 (28-nm T)

DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S -Ph.D. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include hardware security.

Email mim455@hanyang.ac.kr

M.S. Candidates

Ji-Ho Kim

Research Interests High PSRR DPLL

Tape-out Schedule2023.12 (65-nm T), 2023.11 (28-nm S)

DetailsReceived a B.S. degree in electrical engineering from Chosun University, Gwangju, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).

Email wlgh654@hanyang.ac.kr

Dong-Hoe Heo

Research Interests Wide-range PI-based CDR

Tape-out Schedule2024.06 (28-nm T)

AchievementsICEIC'24 Best Paper Award - Gold Prize

DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include clock and data recovery (CDR) circuit design.

Email ehdghl97@hanyang.ac.kr

Kyu-Ran Park

Research InterestsHigh-performance DPLL

Tape-out Schedule2023.11 (65-nm T)

AchievementsCASS Best Design Award

DetailsReceived a B.S. degree in electrical engineering from Cheongju University, Cheongju, South Korea. She is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. She joined LX Semicon, Seoul, South Korea, in 2015, where she was involved in the YPD team. Her research interests include analog and digital circuit designs of phase-locked-loop (PLL).

Emaillan2137@hanyang.ac.kr

Sang-Hyun Ok

Research InterestsCDR, PAM4 receiver

Tape-out Schedule2024.06 (28-nm T), 2024.09 (40-nm T)

DetailsReceived a B.S. degree in the school of electronics and communication engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a Master's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He joined LX Semicon, Seoul, South Korea in 2016, where he was involved in the LCD DDI team. His research interests include digital and analog circuit design of Clock and Data Recovery (CDR) and digital circuit design of PAM4 Receiver with adaptive decision feedback equalizer.

Emailnoradlll@hanyang.ac.kr

Dong-Hyun Lee

Research InterestsAI hardware design and PIM

Tape-out Schedule2024.05 (28-nm T)

DetailsReceived a B.S. degree in the school of Electrical and Electronic Engineering at Dankook University, jukjeon, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Emaildhlee1415@hanyang.ac.kr

Jae-Hyeon Pyeon

Research InterestsHigh-performance DPLL

Tape-out Schedule2023.07 (28-nm S)

DetailsPursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He will join the HPIC Design Lab. in the fall semester of 2024. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).

Emailccomo7004@hanyang.ac.kr

So-Yeon Kwon

Research InterestsDigital PIM

Tape-out Schedule2024.

DetailsReceived a B.S. degree in the school of Applied Physics at Hanyang University, Ansan, South Korea. She is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include artificial intelligence hardware design and processing in memory (PIM).

Emailsykwon00@hanyang.ac.kr

In-Ho Han

Research InterestsPLL

Tape-out Schedule2024.

DetailsReceived a B.S. degree in electrical engineering from Gachon University, Sungnam, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).

Emailinho0303@hanyang.ac.kr

Seung-Hwan Gong

Research InterestsCDR, DSP-based Receiver

Tape-out Schedule2024.

DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests interests include CDR, DSP-based Receiver.

Emailfire051324@gmail.com

Dong-Ho Kim

Research InterestsDSP-based Transmitter

Tape-out Schedule2024.

DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests interests include DSP-DAC based transmitter.

Emaildpdl112@hanyang.ac.kr

Open Positions.

Research Interests

Tape-out Schedule

Achievements

Details

Email

Undergraduate Researchers

Jae-Gun Lee

Research InterestsDSP-based Receiver

Tape-out Schedule2023.11 (28-nm S, 65-nm T), 2024.09 (40-nm T)

Achievements2023 SCCUD 구두 발표 최우수상, ICEIC'24

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Emaildlworjs@hanyang.ac.kr

Min-Gwon Song

Research InterestsPIM and design automation

Achievements2023 SCCUD 구두 발표 최우수상, DAC'24

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Emailllimsg150@hanyang.ac.kr

Jee-Hyun Kwon

Research InterestsPAM4 Receiver (DSP-based Link)

Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S)

Achievements2023 SCCUD 포스터 발표 대상, KCS'24

Details Currently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizer and PAM4 receiver (DSP-based Link).

Emailbornin321@hanyang.ac.kr

Yu-Jin Byeon

Research InterestsTime-Interleaved SAR ADC, DSP-based Receiver

Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S), 2024.06 (28-nm T)

Achievements2023 SCCUD 포스터 발표 대상, KCS'24

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizer and PAM4 receiver (DSP-based Link).

Emailbyj8629@hanyang.ac.kr

Dong-Eun Lee

Research InterestsDSP-based Transmitter

Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S), 2024.09 (40-nm T)

Achievements2023 SCCUD 포스터 발표 대상, KCS'24

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizers and PAM4 receiver (DSP-based Link).

Emaildms2021@hanyang.ac.kr

Seung-Mo Jin

Research InterestsDSP-based Transmitter

Achievements2023 SCCUD 구두 발표 최우수상, ICEIC'24

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Emailvictorymo@hanyang.ac.kr

Woo-Suk Jung

Research InterestsAI hardware design and PIM (2T DRAM)

Tape-out Schedule2024.07 (28-nm S)

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).

Emailwjd5952@hanyang.ac.kr

Jong-Hoon Park

Research InterestsAI hardware design and Digital PIM

Tape-out Schedule

DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and Digital processing in memory (Digital PIM).

Emailhoon765@hanyang.ac.kr

Open Positions. No prerequisite!

Research Interests

Tape-out Schedule

Achievements

Details

Email

Undergraduate Internship

Hanyang University Erica

4학년

3학년

이진호 (pim)

정보성 (analog)

이도형 (CDR)

최재현 (analog)

원지섭 (analog)

박문석 (pim)

박계륜 (tbd)

최재진 (tbd)

김재식 (tbd)

2학년

Indian Institutes of Technology

K Vasanthakumaaran

Sneha Das

Devarsh Bhandari

Open Positions. No prerequisite!

Alumni

In-Woo Jang (M.S. @ KAIST)

Geun-Young Yoo (M.S.-Ph.D. @ Hanyang University)

Tae-Hyun Kim (M.S.-Ph.D. @ POSTECH)

Seung-Wan Han (ASML)

Woo-Suk Jung (@ Yonsei University)

Dong-Eun Lee (Samsung Electronics)

Publications

2024

Journal 2024

2022

...

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

  • IEEE Access
  • D. Lee K. Park J. Han M.-S. Choo
  • Design Methodology Ring Oscillators Voltage-Controlled CMOS Technologies

2021

...

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier with Real-Time Offset Tracking using Time-Division Dual Calibration

  • IEEE Journal of Solid-State Circuits (JSSC)
  • M.-S. Choo S. Kim H.-G. Ko S.-Y. Cho K. Park J. Lee S. Shin H. Chi D.-K. Jeong
  • PVT Variation Injection-Locked Clock Multiplier Offset Tracking
...

A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS

  • IEEE Journal of Solid-State Circuits (JSSC)
  • K. Park K. Lee S.-Y. Choo J. Lee J. Hwang M.-S. Choo D.-K. Jeong
  • Continuous-Rate Digital CDR Frequency Acquisition 65-nm CMOS

2020

...

Review of Injection-Locked Oscillators

  • Journal of Semiconductor Engineering (JSE)
  • M.-S. Choo D.-K. Jeong
  • Injection-Locked Oscillators Review Frequency Stability

2019

...

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response

  • IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II)
  • M.-S. Choo Y. Song S.-Y. Cho H.-G. Ko K. Park D.-K. Jeong
  • Injection-Locked PLL Phase Domain Injection Strength 15-GHz
...

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology

  • IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II)
  • M.-S. Choo K. Park H.-G. Ko S.-Y. Cho K. Lee D.-K. Jeong
  • Half-Rate Injection-Locked CDR Path Mismatch 28-nm CMOS
...

A Current-Mode Digital AOT 4-Phase Buck Voltage Regulator

  • IEEE Solid-State Circuits Letters (SSC-L)
  • M. Choi C.-H. Kye J. Oh M.-S. Choo D.-K. Jeong
  • Current-Mode Digital AOT 4-Phase Voltage Regulator
...

A 4-to-20Gb/s 1.87 pJ/b referenceless digital CDR with unlimited frequency detection capability in 65nm CMOS

  • IEEE Symposium on VLSI Circuits (VLSIC)
  • K. Park K. Lee S.-Y. Cho J. Lee J. Hwang M.-S. Choo D.-K. Jeong
  • Referenceless Digital CDR Frequency Detection 65nm CMOS
...

A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm2 Controller and 80ns Recovery Time

  • IEEE International Solid-State Circuits Conference (ISSCC)
  • M. Choi C.-H. Kye J. Oh M.-S. Choo D.-K. Jeong
  • Synthesizable Digital AOT 4-Phase Buck Recovery Time

2018

...

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop

  • IEEE Asian Solid-State Circuits Conference (A-SSCC) invited to JSSC
  • M.-S. Choo H.-G. Ko S.-Y. Cho K. Lee D.-K. Jeong
  • Half-Rate Injection-Locked Clock and Data Recovery Timing-Margin
...

An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter

  • IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II)
  • M.-S. Choo H.-G. Ko S.-Y. Cho K. Lee D.-K. Jeong
  • Injection-Timing Tracking Loop RO-based PLL Integrated Jitter
...

A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection

  • IEEE Transactions on Circuits and Systems-I: Regular Links (TCAS-I)
  • S.-Y. Cho S. Kim M.-S. Choo H.-G. Ko J. Lee W. Bae D.-K. Jeong
  • Subharmonically Injection-Locked All-Digital PLL Dual-Edge Switched Injection

2017

...

A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel

  • IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II)
  • K. Park J. Lee K. Lee M.-S. Choo S. Jang S.-H. Chu S. Kim D.-K. Jeong
  • Video Interface Receiver Stream Clock Loss Channel
...

A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration

  • IEEE International Solid-State Circuits Conference (ISSCC)
  • S. Kim H.-G. Ko S.-Y. Cho J. Lee S. Shin M.-S. Choo H. Chi D.-K. Jeong
  • Injection-Locked ADPLL Integrated Jitter Time-Division Calibration

2016

...

A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

  • Journal of Semiconductor Technology and Science (JSTS)
  • S. Kim S. Jang S.-Y. Cho M.-S. Choo G.-S. Jeong W. Bae D.-K. Jeong
  • Integrated Jitter Injection-Locked Ring PLL Charge-Stored Injection
...

A theoretical analysis of phase shift in pulse injection-locked oscillators

  • IEEE International Symposium on Circuits and Systems (ISCAS)
  • J. Lee S. Kim M.-S. Choo S.-Y. Cho H.-G. Ko D.-K. Jeong
  • Theoretical Analysis Phase Shift Pulse Injection-Locked Oscillators

2015

...

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

  • European Solid-State Circuits Conference (ESSCIRC)
  • S.-Y. Cho S. Kim M.-S. Choo J. Lee H.-G. Ko S. Jang S.-H. Chu W. Bae Y. Kim D.-K. Jeong
  • Subharmonically Injection-Locked All-Digital PLL Complementary Switched 5-GHz

2024

...
Modeling of DSP-Based Receiver and Analysis Data Phase With Stochastic Method

2024.01

  • KCS 2024
  • J.-H. Kwon T.-H. Kim M.-S. Choo
  • KEYWORDD
...
Technology of Channel Equalization at the Receiver in 28nm CMOS

2024.01

  • KCS 2024
  • D.-E. Lee T.-H. Kim M.-S. Choo
  • KEYWORDD
...
Design of PAM4 Transmitter in 28-nm CMOS Technology

2024.01

  • KCS 2024
  • Y.-J. Byeon M.-S. Choo
  • KEYWORDD
...
An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery

2024.01

  • ICEIC 2024
  • D.-H. Heo T.-H. Kim K.-H. Lee M.-S. Choo
  • KEYWORDD
...
Hardware and Software Co-Simulation Methodology for Processing-In-Memory Bitcell application

2024.01

  • ICEIC 2024
  • J.-G. Lee S.-U. Kang M.-S. Choo
  • KEYWORDD
...
Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks

2024.01

  • ICEIC 2024
  • S.-M. Jin S.-U. Kang M.-S. Choo
  • KEYWORDD
...
Late Breaking Results: A General Purpose Compute-in-Memory Architecture with ADC-Awared Neural Networks

2024.02

  • DAC: LBR 2024
  • M.-G. Song S.-U. Kang M.-S. Choo
  • KEYWORD
...
Vertical AND Cell Package : AND CiM 을 통한 BNN 운용 방법론

2024.05

  • 2024 SOC 학술대회
  • S.-M. Jin S.-U. Kang M.-S. Choo
  • KEYWORDD
...
A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-1 Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural Networks

2024.05

  • ISOCC 2024
  • S.-U. Kang S.-M. Jin M.-G. Song D.-H. Lee W.-S. Jung M.-S. Choo
  • KEYWORD
...
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology

2024.06

  • ASSCC 2024
  • H.-S. Choi J.-G. Lee K.-H. Lee D. Koh J.-W. Sull H.-R. Do C.-H. Kye D.-K. Jeong M.-S. Choo
  • KEYWORD
...
Late Breaking Results: A General Purpose Compute-in-Memory Architecture with ADC-Awared Neural Networks

2024.06

  • DAC (WiP)
  • M.-G. Song S.-U. Kang M.-S. Choo
  • KEYWORDD

2023

...
Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application

2023.02

  • ICEIC
  • S.-U. Kang J.-W. Han M.-S. Choo
  • Radiation-Hardened Processing-In-Memory Crossbar Array Space Application
...
Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Inside Digital Filter

2023.02

  • ICEIC
  • I.-W. Jang M.-S. Choo
  • Phase Control Digital Phase-Locked Loop Loop Delay Digital Filter
...
Phase Domain Response 분석을 통한 Injection-Locked Oscillator의 Locking Point 예측

2023.06

  • 2023 하계학술대회
  • G.-Y. You S.-W. Han J.-H. Kwon D.-E Lee Y.-J Byeon M.-S. Choo
  • KEYWORD
...
PDR 기반 Injection Point에 따른 Injection-Locked Oscillator의 Locking Time 분석

2023.06

  • 2023 하계학술대회
  • G.-Y. You S.-W. Han J.-G. Lee M.-G. Song M.-S. Choo
  • KEYWORD
...
Analysis of Channel Equalization on High-Speed Serial Data Communication

2023.06

  • 2023 하계학술대회
  • T.-H. Kim D.-H. Heo J.-H. Lee S.-M. Jin M.-S. Choo
  • KEYWORD
...
IGA: A General Purpose Compute-in-Memory Architecture with ADC-Awared Neural Networks

2023.12

  • DATE: LBR 2024
  • M.-G. Song S.-U. Kang M.-S. Choo
  • KEYWORD

2024

...

출원| 출원완료| KR · P20240060OP

데이터 처리 장치 및 그 제어 방법

  • M.-G. Song S.-U. Kang S.-Y. Kim M.-S. Choo
...

출원| 출원완료| KR · P20240316OP

삼진/이진 신경망용 단일 종단 및 워드라인 분할 6T 정적 램 기반 ADC 없는 프로세싱 인 메모리 가속기

  • S.-U. Kang M.-G. Song S.-Y. Kim M.-S. Choo
...

출원| 출원완료| KR · P20240332OP

주입 잠금 발진 장치, 상기 주입 잠금 발진 장치를 이용한 위상 잠금 루프 회로 및 이의 제어 방법

  • K.-R. Park J.-H. Kim I.-W. Jang M.-S. Choo

Teaching

Courses
  • ITE4003 : SOC Design (Undergraduate, Fall 2022)
  • EEN3007: Advanced Electronic Circuit and Laboratory (Undergraduate, Fall 2022)
  • EEN3007: Advanced Electronic Circuit and Laboratory (Undergraduate, English, Fall 2022)
  • EEN3001: Electronic Engineering Capstone Design1 (Undergraduate, Fall 2022)
  • ELE2003: Circuit Theory (Undergraduate, Spring 2022)
  • COE3051: Engineering Mathematics 1 (Undergraduate, English, Spring 2022)
  • EEN3003: Electrical Engineering Lab Practice 1 (Undergraduate, Spring 2022)
  • EEN4006: Electrical Engineering Lab Practice 3 (Undergraduate, Spring 2022)
  • VCC1001: IC-PBL and Visioning (Undergraduate, Spring 2022)

Contact

  • +82-31-400-5193
  • mschoo@hanyang.ac.kr
  • 55, Hanyangdaehak-ro, Sangnok-gu, Ansan-si, Gyeonggi-do, Republic of Korea, RM #309, Engineering Building III
  • Wed. 09:00 ~ 10:00, and by appointment.