Chip Gallery

2T eDRAM PIM
2T eDRAM PIM
  • Date: Nov. (65-nm T)'24
  • Designer: Dong-Hyun Lee
  • Description: Digital Analog revision
3T eDRAM PIM
3T eDRAM PIM
  • Date: Nov. (65-nm T)'24
  • Designer: Dong-Hyun Lee
  • Description: Digital Analog revision
PI ADPLL
PI ADPLL
  • Date: Oct. (65-nm T)'24
  • Designer: Kyu-Ran Park
  • Description: N/A
ILO-based PUF
ILO-based PUF
  • Date: Oct. (65-nm T)'24
  • Designer: Kang-Min Kim
  • Description: Analog revision
ADC DSP RX
ADC-based DSP RX
  • Date: Oct. (40-nm T)'24
  • Designer: Sang-Hyun Ok
  • Description: failed
Oversampling PLL
Oversampling PLL
  • Date: Oct. (40-nm T)'24
  • Designer: Ji-Ho Kim
  • Description: N/A
3T eDRAM PIM
3T eDRAM PIM
  • Date: Jul (65-nm T)'24
  • Designer: Woo-Suk Jeong
  • Description: failed
2T eDRAM PIM
2T eDRAM PIM
  • Date: May (65-nm T)'24
  • Designer: Dong-Hyun Lee
  • Description: failed
ILO-based PUF
ILO-based PUF
  • Date: May (65-nm T)'24
  • Designer: Kang-Min Kim
  • Description: failed
PI-based CDR
PI-based CDR
  • Date: June (28-nm T)'24
  • Designer: Dong-Hoe Heo
  • Description: N/A
TI SAR ADC
TI SAR ADC
  • Date: June (28-nm T)'24
  • Designer: Yu-Jin Byeon
  • Description: failed
Supply Noise Insensitive ADPLL
Supply Noise Insensitive ADPLL
  • Date: Dec (65-nm T)'23
  • Designer: N/A
  • Description: N/A
ADPLL ILO Calibration
ADPLL ILO Calibration
  • Date: Dec (65-nm T)'23
  • Designer: N/A
  • Description: failed
SRAM PIM Accelerator
SRAM PIM Accelerator
  • Date: Dec (65-nm T)'23
  • Designer: Shin-Uk Kang
  • Description: N/A
Adaptive Gain Controlled DPLL
Adaptive Gain Controlled DPLL
  • Date: Dec (65-nm T)'23
  • Designer: In-Woo Jang
  • Description: failed
TX-PAM4-DRV
TX-PAM4-DRV
  • Date: July (28-nm S)'23
  • Designer: N/A
  • Description: N/A
High-Speed Equalizer
High-Speed Equalizer
  • Date: July (28-nm S)'23
  • Designer: N/A
  • Description: N/A
ADPLL
ADPLL
  • Date: Jan (28-nm S)'23
  • Designer: Ji-Ho Kim
  • Description: N/A
Injection Lock Oscillator (ILO)
Injection Lock Oscillator (ILO)
  • Date: Jan (28-nm S)'23
  • Designer: Geun-Young Yu
  • Description: N/A
Flash ADC
Flash ADC
  • Date: Jan (28-nm S)'23
  • Designer: Dong-Hoe Heo
  • Description: N/A
Clock Generator
Clock Generator
  • Date: ISSCC'17, JSSC'21
  • Designer: N/A
  • Description: N/A
Clock and Data Recovery (CDR)
Clock and Data Recovery (CDR)
  • Date: VLSI'19, JSSC'21
  • Designer: N/A
  • Description: N/A
Clock Generator
Clock Generator
  • Date: TCAS-II'19
  • Designer: N/A
  • Description: N/A
Power Regulator
Power Regulator
  • Date: ISSCC'19, SSC-L'19
  • Designer: N/A
  • Description: N/A
CDR
CDR
  • Date: ASSCC'18, JSSC'19
  • Designer: N/A
  • Description: N/A
Clock Generator
Clock Generator
  • Date: TCAS-II'18
  • Designer: N/A
  • Description: N/A
Video Interface Receiver
Video Interface Receiver
  • Date: TCAS-II'17
  • Designer: N/A
  • Description: N/A
Clock Generator
Clock Generator
  • Date: ESSCIRC'15, TCAS-I'18
  • Designer: N/A
  • Description: N/A
Clock Gen. & CDR
Clock Gen. & CDR
  • Date: Failed'17
  • Designer: N/A
  • Description: N/A
CDR
CDR
  • Date: Failed'16
  • Designer: N/A
  • Description: N/A
CDR
CDR
  • Date: Failed'15
  • Designer: N/A
  • Description: N/A