Feb.2024
Welcome! S.-H. Ok and D.-H. Lee have joined the HPIC design lab. as a candidate for a Master's degree.
Feb.2023
Welcome! D.-H. Heo and K.-R. Park have joined the HPIC design lab. as a candidate for a Master's degree.
Feb.2023
Welcome! S.-U. Kang and K.-M. Kim have joined the HPIC design lab. as a candidate for an M.S.-Ph.D.
Aug.2022
Welcome! J. Kim has joined the HPIC design lab. as a candidate for a Master's degree.
Mar.2022
HPIC Design Lab. website is open.
Mar.2022
Professor Min-Seong Choo is appointed.
We focus on optimizing integrated circuits and systems for high-performance computing.
2T eDRAM PIM
May (65-nm T)'24
ILO-based PUF
May (65-nm T)'24
PI-based CDR
June (28-nm T)'24
TI SAR ADC
June (28-nm T)'24
Supply Noise Insensitive ADPLL
Dec (65-nm T)'23
ADPLL ILO Calibration
Dec (65-nm T)'23
SRAM PIM Accelerator
Dec (65-nm T)'23
Adaptive Gain Controlled DPLL
Dec (65-nm T)'23
TX-PAM4-DRV
July (28-nm S)'23
High-Speed Equalizer
July (28-nm S)'23
ADPLL
Apr (28-nm S)'23
ADPLL
Jan (28-nm S)'23
Injection Lock Oscillator (ILO)
Jan (28-nm S)'23
Flash ADC
Jan (28-nm S)'23
Clock Generator
ISSCC'17, JSSC'21
Clock and Data Recovery (CDR)
VLSI'19, JSSC'21
Clock Generator
TCAS-II'19
Power Regulator
ISSCC'19, SSC-L'19
CDR
ASSCC'18, JSSC'19
Clock Generator
TCAS-II'18
Video Interface Receiver
TCAS-II'17
Clock Generator
JSTS'16
Clock Generator
ESSCIRC'15, TCAS-I'18
Clock Gen. & CDR
Failed'17
CDR
Failed'16
CDR
Failed'15
Apr. 2024 - Mar. 2027
Development of High-Speed, Low-Power, and Low-Noise Clocking Network Systems for Optical Communication Chiplets
National Research Fund (NRF) of Korea; 우수신진연구
Apr. 2022 - Dec. 2024
Development of low-power/high-performance 2T DRAM PIM cell, integrated circuits, and architecture
National Research Fund (NRF) of Korea
Sep. 2022 - Sep. 2023
Design Methodology of High-Performance Integrated Circuits based on Reinforcement Learning
Quallitas Semiconductor, completed
Sep. 2022 - Sep. 2023
Development of High PSRR Low Phase Noise Voltage-Controlled Oscillator (VCO)
ACONIC Inc., completed
Jul. 2022 - Feb. 2025
반도체전공트랙사업
KIAT
Mar. 2022 - Aug. 2027
BK21 (고신뢰성 에너지용 지능형 시스템반도체 교육연구단)
Ministry of Education
Mar. 2022 - Dec. 2025
AI Hardware Center (인공지능 반도체 융합연구센터)
National Research Fund (NRF) of Korea
Sep. 2022 - Feb. 2024
강화학습 기반 고성능 아날로그 집적회로 설계 및 측정 플랫폼 개발
National Research Fund (NRF) of Korea, completed
Mar. 2022 - Feb. 2023
신임교원 정착연구지원사업
HYU, completed
전력반도체 인력 양성센터
...
Research Interests
Details
I serve as a reviewer for various journals, including the IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I/II, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and IEEE ACCESS.
Open PositionsPlease contact to Min-Seong
(mschoo@hanyang.ac.kr).
And, think about your future after receiving a degree;
Ph.D./Postdoc at HPIC, Ph.D./Postdoc at another
institution (domestic/international), and finding a job
(domestic/international).
Research Interests AI hardware design and PIM
Tape-out Schedule2023.12 (65-nm T), 2024.05 (28-nm T)
AchievementsICEIC'23, ICEIC'24
DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S -Ph.D. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Email ksu2068@hanyang.ac.kr
Research Interests Physically Unclonable Function (PUF)
Tape-out Schedule2024.05 (28-nm T)
DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S -Ph.D. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include hardware security.
Email mim455@hanyang.ac.kr
Research Interests High PSRR DPLL
Tape-out Schedule2023.12 (65-nm T), 2023.11 (28-nm S)
DetailsReceived a B.S. degree in electrical engineering from Chosun University, Gwangju, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).
Email wlgh654@hanyang.ac.kr
Research Interests Wide-range PI-based CDR
Tape-out Schedule2024.06 (28-nm T)
AchievementsICEIC'24 Best Paper Award - Gold Prize
DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include clock and data recovery (CDR) circuit design.
Email ehdghl97@hanyang.ac.kr
Research InterestsHigh-performance DPLL
Tape-out Schedule2023.11 (65-nm T)
AchievementsCASS Best Design Award
DetailsReceived a B.S. degree in electrical engineering from Cheongju University, Cheongju, South Korea. She is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. She joined LX Semicon, Seoul, South Korea, in 2015, where she was involved in the YPD team. Her research interests include analog and digital circuit designs of phase-locked-loop (PLL).
Emaillan2137@hanyang.ac.kr
Research InterestsCDR, PAM4 receiver
Tape-out Schedule2024.06 (28-nm T), 2024.09 (40-nm T)
DetailsReceived a B.S. degree in the school of electronics and communication engineering at Hanyang University, Ansan, South Korea. He is currently pursuing a Master's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He joined LX Semicon, Seoul, South Korea in 2016, where he was involved in the LCD DDI team. His research interests include digital and analog circuit design of Clock and Data Recovery (CDR) and digital circuit design of PAM4 Receiver with adaptive decision feedback equalizer.
Emailnoradlll@hanyang.ac.kr
Research InterestsAI hardware design and PIM
Tape-out Schedule2024.05 (28-nm T)
DetailsReceived a B.S. degree in the school of Electrical and Electronic Engineering at Dankook University, jukjeon, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Emaildhlee1415@hanyang.ac.kr
Research InterestsHigh-performance DPLL
Tape-out Schedule2023.07 (28-nm S)
DetailsPursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. He will join the HPIC Design Lab. in the fall semester of 2024. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).
Emailccomo7004@hanyang.ac.kr
Research InterestsDigital PIM
Tape-out Schedule2024.
DetailsReceived a B.S. degree in the school of Applied Physics at Hanyang University, Ansan, South Korea. She is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include artificial intelligence hardware design and processing in memory (PIM).
Emailsykwon00@hanyang.ac.kr
Research InterestsPLL
Tape-out Schedule2024.
DetailsReceived a B.S. degree in electrical engineering from Gachon University, Sungnam, South Korea. He is currently pursuing a M.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include analog and digital circuit designs of phase-locked-loop (PLL).
Emailinho0303@hanyang.ac.kr
Research InterestsCDR, DSP-based Receiver
Tape-out Schedule2024.
DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests interests include CDR, DSP-based Receiver.
Emailfire051324@gmail.com
Research InterestsDSP-based Transmitter
Tape-out Schedule2024.
DetailsReceived a B.S. degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests interests include DSP-DAC based transmitter.
Emaildpdl112@hanyang.ac.kr
Research Interests
Tape-out Schedule
Achievements
Details
Research InterestsDSP-based Receiver
Tape-out Schedule2023.11 (28-nm S, 65-nm T), 2024.09 (40-nm T)
Achievements2023 SCCUD 구두 발표 최우수상, ICEIC'24
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Emaildlworjs@hanyang.ac.kr
Research InterestsPIM and design automation
Achievements2023 SCCUD 구두 발표 최우수상, DAC'24
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Emailllimsg150@hanyang.ac.kr
Research InterestsPAM4 Receiver (DSP-based Link)
Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S)
Achievements2023 SCCUD 포스터 발표 대상, KCS'24
Details Currently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizer and PAM4 receiver (DSP-based Link).
Emailbornin321@hanyang.ac.kr
Research InterestsTime-Interleaved SAR ADC, DSP-based Receiver
Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S), 2024.06 (28-nm T)
Achievements2023 SCCUD 포스터 발표 대상, KCS'24
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizer and PAM4 receiver (DSP-based Link).
Emailbyj8629@hanyang.ac.kr
Research InterestsDSP-based Transmitter
Tape-out Schedule2023.07 (28-nm S), 2023.11 (28-nm S), 2024.09 (40-nm T)
Achievements2023 SCCUD 포스터 발표 대상, KCS'24
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. Her research interests include adaptive equalizers and PAM4 receiver (DSP-based Link).
Emaildms2021@hanyang.ac.kr
Research InterestsDSP-based Transmitter
Achievements2023 SCCUD 구두 발표 최우수상, ICEIC'24
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Emailvictorymo@hanyang.ac.kr
Research InterestsAI hardware design and PIM (2T DRAM)
Tape-out Schedule2024.07 (28-nm S)
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and processing in memory (PIM).
Emailwjd5952@hanyang.ac.kr
Research InterestsAI hardware design and Digital PIM
Tape-out Schedule
DetailsCurrently pursuing a Bachelor's degree in the school of electrical engineering at Hanyang University, Ansan, South Korea. His research interests include artificial intelligence hardware design and Digital processing in memory (Digital PIM).
Emailhoon765@hanyang.ac.kr
Research Interests
Tape-out Schedule
Achievements
Details
4학년
3학년
이진호 (pim)
정보성 (analog)
이도형 (CDR)
최재현 (analog)
원지섭 (analog)
박문석 (pim)
박계륜 (tbd)
최재진 (tbd)
김재식 (tbd)
2학년
K Vasanthakumaaran
Sneha Das
Devarsh Bhandari
In-Woo Jang (M.S. @ KAIST)
Geun-Young Yoo (M.S.-Ph.D. @ Hanyang University)
Tae-Hyun Kim (M.S.-Ph.D. @ POSTECH)
Seung-Wan Han (ASML)
Woo-Suk Jung (@ Yonsei University)
Dong-Eun Lee (Samsung Electronics)
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier with Real-Time Offset Tracking using Time-Division Dual Calibration
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology
A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop
An optimum injection-timing tracking loop for 5-GHz, 1.13-mW/GHz RO-based injection-locked PLL with 152-fs integrated jitter
A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection
A 55.1 mW 1.62-to-8.1 Gb/s video interface receiver generating up to 680 MHz stream clock over 20 dB loss channel
A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and −65dBc reference spur using time-division dual calibration
A 285-fsrms Integrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection
출원| 출원완료| KR · P20240060OP
데이터 처리 장치 및 그 제어 방법
출원| 출원완료| KR · P20240316OP
삼진/이진 신경망용 단일 종단 및 워드라인 분할 6T 정적 램 기반 ADC 없는 프로세싱 인 메모리 가속기
출원| 출원완료| KR · P20240332OP
주입 잠금 발진 장치, 상기 주입 잠금 발진 장치를 이용한 위상 잠금 루프 회로 및 이의 제어 방법